Field of the Invention
The invention relates to a circuit configuration and a method for the testing of storage cells which are disposed in the form of a matrix and which can be driven through word and bit lines, each bit line being assigned an evaluator circuit dividing the bit line into two identical bit line halves.
In recent years the increase in the number of storage cells in a semiconductor memory has led to an enormous lengthening of the test time required to test a semiconductor memory. Whereas, for example, a DRAM with a storage capacity of 4 kB could previously be adequately tested in a test time of 3 to 20 seconds (depending upon the type and number of test patterns used and other test conditions), the test time of a modern 1MB-DRAM is in the order of 20 minutes.
Various measures for shortening the test time have already been disclosed. For example, European Application No. 0 186 040, corresponding to allowed U.S. application Ser. No. 811,932 proposes that a semiconductor memory be internally divided into a plurality of identical blocks and that these blocks be tested in parallel relative to one another. In practice this permits the test time to be reduced to approximately one-quarter to one-eighth of the time previously required.
U.S. Pat. No. 4,055,754 proposes that all of the storage cells of a complete word line be tested in parallel with respect to time, and that a specified analysis circuit within the semiconductor memory be used for this purpose. Despite a substantial reduction in test time, this solution is disadvantageous since it requires an analysis circuit composed of at least three logic gates, two of the gates requiring a number of inputs which is equal to the number of existing word lines. The construction of such a device leads to a very great additional service area requirement, which contradicts the general trend to miniaturize circuits.
It is accordingly an object of the invention to provide a circuit configuration and a method for the testing of storage cells, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type and which permits storage cells to be tested with a short time outlay and a minimum additional surface area requirement.